Abstract: An efficient architecture of vector-radix 2×2 (VR2×2) two dimensional fast Fourier transform (2D-FFT) algorithm for hardware implementation is presented using decimation-in-time. The data of N×N points were divided into four parts to allow simultaneous access to four data needed by the unit of VR2×2 butterfly. The memory assignment was in-place to minimize the memory size, and the access of conflict free allowed four memory banks to be accessed simultaneously. The data address generation algorithms were proposed. The coordinated rotation digital computer (CORDIC) algorithm was used to generate the twiddle factors to save the memories. For data of N×N points, the proposed architecture only costs (N²/2)(lb N-1) clock periods to complete the two dimensional DFT transform. The comparison of computing time with that needed by other methods shows the effectiveness of the new architecture.