Abstract: A radiation hardened-by-design for mitigating single event transient (SET) in bias circuit is proposed in this paper. By adding a SET suppressor circuit consisting of a resistor, a PMOS and NMOS, the bias circuit achieves excellent SET immunity. To confirm the obtained hardness, conventional and proposed hardened bias circuits were designed using SIMC 130 nm CMOS technology. Simulation results show that, compared with conventional bias circuit, the disturbance of voltage and mirror current induced by SET in proposed hardened bias circuit is reduced by 80.6% and 81.2%, respectively. In addition, the added SET suppressor circuit has the advantageous like that, no additional SET sensitive node is introduced, no additional power consumption is induced during normal operation and it occupies small chip area.