Abstract: To suppress the quantization noise from Σ-△ modulator,this paper proposed a frequency synthesizer based on multi-phase fractional divider. This structure can avoid glitch while consuming less power because all main block working on lower frequency. 50% duty cycle input also does not needed here. Through comparing, this technique can reduce 12 dB output phase noise of a 1 MHz bandwidth Σ-△ fractional-N frequency synthesizer. This synthesizer is implemented in UMC 0.18 μm CMOS process, the post-layout simulation shows that it can meet the requirement of DVB-H system.