High-Speed VLSI Architecture Design for 2-D Discrete Wavelet Transform for JPEG 2000 Standard

A high-speed architecture that performed a 2-D discrete wavelet transform for JPEG 2000 standard was proposed. The architecture is designed for lifting based DWT. The architecture consists of two row filters, two column filters, and three memory modules. Each processor contained two adders, one right shifter. And they processed the signals in parallel way. The whole architecture was optimized in the pipeline design way to increase the transform speed, and achieve higher hardware utilization. The architecture had been implemented and simulated in behavioral VHDL. The architecture could be used as a compact and independent IP core for JPEG 2000 VLSI implementation and various real-time image/video applications.