Study on Scheduling Algorithms Constrained by Behavioral Delay

The methodology of synthesis of synchronizing statements in VHDL is studied to automatically synthesize behavioral timing generated by design iteration, so as to improve the consistency of timing between the behavioral design and synthesis result. A new scheduling algoritm is presented. The delay time is considered as delay constraints in the algorithm. Scheduling model and corresponding algorithm are also presented. A heuristic method is applied in the algorithm to ensure the algorithm to jump out from local optimization and reach the approximate optimization in polynomial time complexity. It can be concluded from the experimental results that the scheduling algorithm can efficiently synthesize the delay statements and the synthesis result of behavioral design can be more consistent in timing. A convenient means has also been presented to set the timing constraints for synthesis, thus the manual interaction in the synthesis process can be decreased, and the design efficiency can be greatly improved.