Low-Complexity Parallel Architecture for Joint Matched Filtering and Timing Recovery in Terahertz Communications

TY - JOUR

T1 - Low-Complexity Parallel Architecture for Joint Matched Filtering and Timing Recovery in Terahertz Communications

AU - Yu, Xindi

AU - Zhao, Liangbin

AU - Shen, Wenqian

AU - Li, Jianguo

AU - Bu, Xiangyuan

N1 - Publisher Copyright: © 1967-2012 IEEE.

PY - 2026/7/1

Y1 - 2026/7/1

N2 - Emerging intelligent transportation systems are driving demand for ultra-fast and reliable wireless communication, pushing physical-layer design toward millimeter-wave (mmWave) and terahertz (THz) bands. However, as critical components of the receiver, conventional matched filtering (MF) and timing recovery (TR) incur high complexity and latency, limiting their applicability in such high-throughput scenarios. To address this, we propose a feedback-based unified parallel architecture for joint MF and TR (PAMT), which integrates timing error compensation into the MF process. PAMT flexibly supports different timing error detection algorithms, such as Oerder & Meyr or Gardner algorithms, to accommodate varying latency and precision requirements. It is optimized for 4x oversampling systems and can be easily generalized to other configurations. Simulations demonstrate the effectiveness and low complexity of PAMT, which is further validated by a hardware implementation on a Xilinx XCVU9P FPGA under 220 GHz, 64QAM, 15 Gbps, and 64-way parallelism, confirming its feasibility for THz communication systems.

AB - Emerging intelligent transportation systems are driving demand for ultra-fast and reliable wireless communication, pushing physical-layer design toward millimeter-wave (mmWave) and terahertz (THz) bands. However, as critical components of the receiver, conventional matched filtering (MF) and timing recovery (TR) incur high complexity and latency, limiting their applicability in such high-throughput scenarios. To address this, we propose a feedback-based unified parallel architecture for joint MF and TR (PAMT), which integrates timing error compensation into the MF process. PAMT flexibly supports different timing error detection algorithms, such as Oerder & Meyr or Gardner algorithms, to accommodate varying latency and precision requirements. It is optimized for 4x oversampling systems and can be easily generalized to other configurations. Simulations demonstrate the effectiveness and low complexity of PAMT, which is further validated by a hardware implementation on a Xilinx XCVU9P FPGA under 220 GHz, 64QAM, 15 Gbps, and 64-way parallelism, confirming its feasibility for THz communication systems.

KW - FPGA

KW - Matched filtering

KW - THz communications

KW - parallel architecture

KW - timing recovery

UR - https://www.scopus.com/pages/publications/105027805847

U2 - 10.1109/TVT.2026.3653468

DO - 10.1109/TVT.2026.3653468

M3 - Article

AN - SCOPUS:105027805847

SN - 0018-9545

VL - 75

SP - 15166

EP - 15170

JO - IEEE Transactions on Vehicular Technology

JF - IEEE Transactions on Vehicular Technology

IS - 7

ER -