SHARP: A Scalable FPGA-Based CNN Accelerator for On-Board Target Detection

On-board target detection demands high computational throughput under stringent energy and memory budgets, thereby necessitating architectures that tightly couple high parallelism to memory-efficient data orchestration. This article presents SHARP, a scalable field-programmable gate array (FPGA)-oriented convolutional neural network (CNN) accelerator tailored for real-time, resource-constrained remote-sensing deployments. SHARP increases sustained concurrency by adopting a packet-based multilevel parallel convolution strategy that reduces intermediate storage while enabling high-degree parallel processing of large multichannel feature maps. Building on this compute fabric, a scalable multilevel parallel CNN compute engine is provided so that the effective parallelism can be tuned to match available digital signal processor (DSP), lookup table, and block random access memory (BRAM) resources; this flexibility enables efficient mapping across devices with different resource budgets. To preserve throughput in practice, an integrated off-chip and on-chip data access strategy combines DDR interleaving with multi-BRAM dislocated caching and ping-pong buffering, thereby improving burst bandwidth utilization and removing read/write conflicts so I/O can be overlapped with computation. A theoretical resource-analysis framework ties these elements together by quantifying achievable parallelism under DSP and BRAM constraints and guiding hardware dimensioning. SHARP is implemented on a Xilinx XC7VX690T. The prototype attains a peak throughput of 1480.95 GOPS at 250 MHz with 20.525 W power and delivers 72.15 GOPS/W energy efficiency while maintaining 98.47% mAP. Compared with reported FPGA YOLO accelerators, these results demonstrate that SHARP achieves a superior tradeoff between throughput and energy efficiency for real-time, on-board remote-sensing applications.