A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping

TY - JOUR

T1 - A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping

AU - Wu, Hao

AU - Chen, Yong

AU - Li, Ming

AU - Zhang, Bingxin

AU - Zhang, Rui

AU - Yuan, Yiyang

AU - Yang, Yiming

AU - Yue, Jinshan

AU - Wang, Xinghua

AU - Li, Xiaoran

AU - Zhang, Feng

N1 - Publisher Copyright: © 1966-2012 IEEE.

PY - 2026/4/1

Y1 - 2026/4/1

N2 - Computing-in-memory (CiM) architecture is considered a technology that promises to alleviate the memory wall problem in artificial intelligence (AI) computing. Previous work on digital CiM macros has achieved significant energy efficiency advantages in supporting approximate calculations of traditional integer (INT)/floating point (FP) data. POSIT is an emerging FP number system. Its main characteristic is that it can approach a good tradeoff between data range and accuracy by flexibly adjusting the mantissa bit width. However, current digital CiM macros lack the ability to support approximate calculations of POSIT data. Given this, we propose a POSIT-approximate-calculation-based CiM macro. The three main contributions of our work are as follows: 1) we improve the original POSIT approximate calculation principle and design a calculation logic circuit based on unsigned Radix8+ final-cycle fusion (FCF); 2) we propose a macro-level approximate calculation control strategy to help the CiM macro find a compromise between calculation performance and calculation error; and 3) we design an activation mantissa alignment skipping (AMAS) unit, to help the hardware skip sparse activation bits when calculating POSIT multiplication. A prototype of the CiM macro was fabricated in a 28-nm complementary metal oxide semiconductor (CMOS) and scored a peak macro energy efficiency of 88.3 TFLOPS/W @ POSIT (8, 2) for a voltage supply of 0.55-1.1 V and an operating frequency of 70-280 MHz, a value 2.12× higher than other state-of-the-art POSIT CiM macros.

AB - Computing-in-memory (CiM) architecture is considered a technology that promises to alleviate the memory wall problem in artificial intelligence (AI) computing. Previous work on digital CiM macros has achieved significant energy efficiency advantages in supporting approximate calculations of traditional integer (INT)/floating point (FP) data. POSIT is an emerging FP number system. Its main characteristic is that it can approach a good tradeoff between data range and accuracy by flexibly adjusting the mantissa bit width. However, current digital CiM macros lack the ability to support approximate calculations of POSIT data. Given this, we propose a POSIT-approximate-calculation-based CiM macro. The three main contributions of our work are as follows: 1) we improve the original POSIT approximate calculation principle and design a calculation logic circuit based on unsigned Radix8+ final-cycle fusion (FCF); 2) we propose a macro-level approximate calculation control strategy to help the CiM macro find a compromise between calculation performance and calculation error; and 3) we design an activation mantissa alignment skipping (AMAS) unit, to help the hardware skip sparse activation bits when calculating POSIT multiplication. A prototype of the CiM macro was fabricated in a 28-nm complementary metal oxide semiconductor (CMOS) and scored a peak macro energy efficiency of 88.3 TFLOPS/W @ POSIT (8, 2) for a voltage supply of 0.55-1.1 V and an operating frequency of 70-280 MHz, a value 2.12× higher than other state-of-the-art POSIT CiM macros.

KW - Approximate calculation

KW - POSIT

KW - Radix8

KW - artificial intelligence (AI)

KW - complementary metal oxide semiconductor (CMOS)

KW - computing-in-memory (CiM)

KW - energy efficiency

KW - final-cycle fusion (FCF)

KW - joint skipping

KW - multiply accumulation (MAC)

KW - neural network (NN)

UR - https://www.scopus.com/pages/publications/105013055478

U2 - 10.1109/JSSC.2025.3590632

DO - 10.1109/JSSC.2025.3590632

M3 - Article

AN - SCOPUS:105013055478

SN - 0018-9200

VL - 61

SP - 1682

EP - 1696

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

ER -