A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

Yiyang Yuan; Bingxin Zhang; Yiming Yang; Yishan Luo; Qirui Chen; Haitao Wang; Qihao Liu; Zhiming Chen; Hao Wu; Jinshan Yue; Shidong Lv; Xinghua Wang; Pui In Mak; Xiaoran Li; Feng Zhang

doi:10.1109/JSSC.2026.3679560

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

Yiyang Yuan
, Bingxin Zhang
, Yiming Yang
, Yishan Luo
, Qirui Chen
, Haitao Wang
, Qihao Liu
, Zhiming Chen
, Hao Wu
, Jinshan Yue
, Shidong Lv
, Xinghua Wang^*
, Pui In Mak
, Xiaoran Li^*
, Feng Zhang^*

^*此作品的通讯作者

集成电路与电子学院

CAS - Institute of Microelectronics
Beijing Institute of Technology
Shandong SinoChip Semiconductors Company Ltd.
University of Macau

科研成果: 期刊稿件 › 文章 › 同行评审

摘要

Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. To address the limitations of previous analog transpose and digital non-transpose SRAM CIM macros, this work features: 1) a cyclic-weight-mapping SRAM array that enables matrix transposition and reuse of MAC circuits during both feed-forward (FF) and back-propagation (BP) phases; 2) a digital CIM architecture employing signed fixed-point mantissa encode and a vector-wise pre-alignment (VWPA) scheme, supporting multiple data formats including INT4/8, FP8, and BF16; and 3) an accurate/approximate dual-mode bit-parallel MAC circuit (DMBP-MAC) designed to provide a tradeoff between computational accuracy and energy efficiency. A fabricated 28-nm 32-kB transpose SRAM CIM macro achieved average energy efficiency of 70.2–285.4 TOPS/W in INT4, 17.5–71.4 TOPS/W in INT8, 51.1–192.3 TFLOPS/W in FP8, and 12.8–48 TFLOPS/W in BF16.

源语言	英语
期刊	IEEE Journal of Solid-State Circuits
DOI	https://doi.org/10.1109/JSSC.2026.3679560
出版状态	已接受/待刊 - 2026

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10.1109/JSSC.2026.3679560

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Yuan, Y., Zhang, B., Yang, Y., Luo, Y., Chen, Q., Wang, H., Liu, Q., Chen, Z., Wu, H., Yue, J., Lv, S., Wang, X., Mak, P. I., Li, X., & Zhang, F. (已接受/印刷中). A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/JSSC.2026.3679560

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title = "A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference",

abstract = "Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. To address the limitations of previous analog transpose and digital non-transpose SRAM CIM macros, this work features: 1) a cyclic-weight-mapping SRAM array that enables matrix transposition and reuse of MAC circuits during both feed-forward (FF) and back-propagation (BP) phases; 2) a digital CIM architecture employing signed fixed-point mantissa encode and a vector-wise pre-alignment (VWPA) scheme, supporting multiple data formats including INT4/8, FP8, and BF16; and 3) an accurate/approximate dual-mode bit-parallel MAC circuit (DMBP-MAC) designed to provide a tradeoff between computational accuracy and energy efficiency. A fabricated 28-nm 32-kB transpose SRAM CIM macro achieved average energy efficiency of 70.2–285.4 TOPS/W in INT4, 17.5–71.4 TOPS/W in INT8, 51.1–192.3 TFLOPS/W in FP8, and 12.8–48 TFLOPS/W in BF16.",

keywords = "Approximate computing, artificial intelligence (AI), computing-in-memory (CIM), floating point (FP), static random-access memory (SRAM)",

author = "Yiyang Yuan and Bingxin Zhang and Yiming Yang and Yishan Luo and Qirui Chen and Haitao Wang and Qihao Liu and Zhiming Chen and Hao Wu and Jinshan Yue and Shidong Lv and Xinghua Wang and Mak, \{Pui In\} and Xiaoran Li and Feng Zhang",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2026",

doi = "10.1109/JSSC.2026.3679560",

language = "English",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

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T1 - A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

AU - Yuan, Yiyang

AU - Zhang, Bingxin

AU - Yang, Yiming

AU - Luo, Yishan

AU - Chen, Qirui

AU - Wang, Haitao

AU - Liu, Qihao

AU - Chen, Zhiming

AU - Wu, Hao

AU - Yue, Jinshan

AU - Lv, Shidong

AU - Wang, Xinghua

AU - Mak, Pui In

AU - Li, Xiaoran

AU - Zhang, Feng

PY - 2026

Y1 - 2026

N2 - Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. To address the limitations of previous analog transpose and digital non-transpose SRAM CIM macros, this work features: 1) a cyclic-weight-mapping SRAM array that enables matrix transposition and reuse of MAC circuits during both feed-forward (FF) and back-propagation (BP) phases; 2) a digital CIM architecture employing signed fixed-point mantissa encode and a vector-wise pre-alignment (VWPA) scheme, supporting multiple data formats including INT4/8, FP8, and BF16; and 3) an accurate/approximate dual-mode bit-parallel MAC circuit (DMBP-MAC) designed to provide a tradeoff between computational accuracy and energy efficiency. A fabricated 28-nm 32-kB transpose SRAM CIM macro achieved average energy efficiency of 70.2–285.4 TOPS/W in INT4, 17.5–71.4 TOPS/W in INT8, 51.1–192.3 TFLOPS/W in FP8, and 12.8–48 TFLOPS/W in BF16.

AB - Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. To address the limitations of previous analog transpose and digital non-transpose SRAM CIM macros, this work features: 1) a cyclic-weight-mapping SRAM array that enables matrix transposition and reuse of MAC circuits during both feed-forward (FF) and back-propagation (BP) phases; 2) a digital CIM architecture employing signed fixed-point mantissa encode and a vector-wise pre-alignment (VWPA) scheme, supporting multiple data formats including INT4/8, FP8, and BF16; and 3) an accurate/approximate dual-mode bit-parallel MAC circuit (DMBP-MAC) designed to provide a tradeoff between computational accuracy and energy efficiency. A fabricated 28-nm 32-kB transpose SRAM CIM macro achieved average energy efficiency of 70.2–285.4 TOPS/W in INT4, 17.5–71.4 TOPS/W in INT8, 51.1–192.3 TFLOPS/W in FP8, and 12.8–48 TFLOPS/W in BF16.

KW - Approximate computing

KW - artificial intelligence (AI)

KW - computing-in-memory (CIM)

KW - floating point (FP)

KW - static random-access memory (SRAM)

UR - https://www.scopus.com/pages/publications/105036246759

U2 - 10.1109/JSSC.2026.3679560

DO - 10.1109/JSSC.2026.3679560

M3 - Article

AN - SCOPUS:105036246759

SN - 0018-9200

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

ER -

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

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