A Novel Time-Division Multiplexing Architecture Revealed by Reconfigurable Synapse for Deep Neural Networks

TY - JOUR

T1 - A Novel Time-Division Multiplexing Architecture Revealed by Reconfigurable Synapse for Deep Neural Networks

AU - Li, Yu Tao

AU - Xu, Kui

AU - Ma, Yu Zhe

AU - Li, Jun Ze

AU - Luo, Yang

AU - Li, Xin Ru

AU - Shen, Peng Hui

AU - Zhao, Lu Yu

AU - Liu, Hang

AU - Ren, Li

AU - Li, De Hui

AU - Peng, Lian Mao

AU - Ding, Li

AU - Ren, Tian Ling

AU - Wang, Yeliang

N1 - Publisher Copyright: © 2025 Wiley-VCH GmbH.

PY - 2025/10/2

Y1 - 2025/10/2

N2 - Deep learning's growing complexity demands advanced AI chips, increasing hardware costs. Time-division multiplexing (TDM) neural networks offer a promising solution to simplify integration. However, it is difficult for current synapse transistors to physically implement TDM networks due to inherent device limitations, hindering their practical deployment in modern systems. Here, a novel graphene/2D perovskite/carbon nanotubes (CNTs) synapse transistor featuring a sandwich structure is presented. This transistor enables the realization of TDM neural networks at the hardware level. In this structure, the 2D perovskite layer, characterized by high ion concentration, serves as a neurotransmitter, thereby enhancing synaptic transmission efficiency. Additionally, the CNTs' field-effect transistors, with their large on-off ratio, demonstrate a wider range of synaptic current changes. The device mechanism is theoretically analyzed using molecular dynamics simulation. Furthermore, the impact of TDM on the scale, power, and latency of neural network hardware implementation is investigated. Qualitative analysis is performed to elucidate the advantages of TDM in the hardware implementation of larger deep learning models. This study offers a new approach to reducing the integration complexity of neural networks hardware implementation, holding significant promise for the development of intelligent nanoelectronic devices in the future.

AB - Deep learning's growing complexity demands advanced AI chips, increasing hardware costs. Time-division multiplexing (TDM) neural networks offer a promising solution to simplify integration. However, it is difficult for current synapse transistors to physically implement TDM networks due to inherent device limitations, hindering their practical deployment in modern systems. Here, a novel graphene/2D perovskite/carbon nanotubes (CNTs) synapse transistor featuring a sandwich structure is presented. This transistor enables the realization of TDM neural networks at the hardware level. In this structure, the 2D perovskite layer, characterized by high ion concentration, serves as a neurotransmitter, thereby enhancing synaptic transmission efficiency. Additionally, the CNTs' field-effect transistors, with their large on-off ratio, demonstrate a wider range of synaptic current changes. The device mechanism is theoretically analyzed using molecular dynamics simulation. Furthermore, the impact of TDM on the scale, power, and latency of neural network hardware implementation is investigated. Qualitative analysis is performed to elucidate the advantages of TDM in the hardware implementation of larger deep learning models. This study offers a new approach to reducing the integration complexity of neural networks hardware implementation, holding significant promise for the development of intelligent nanoelectronic devices in the future.

KW - 2D perovskite

KW - carbon nanotubes

KW - deep neural networks

KW - graphene

KW - reconfigurable synapse

KW - time-division multiplexing architecture

UR - https://www.scopus.com/pages/publications/105010027058

U2 - 10.1002/adma.202420218

DO - 10.1002/adma.202420218

M3 - Article

C2 - 40630032

AN - SCOPUS:105010027058

SN - 0935-9648

VL - 37

JO - Advanced Materials

JF - Advanced Materials

IS - 39

M1 - 2420218

ER -