Hyper-Parallel Superscalar Asynchronous RISC-V Processor Based on Event-Driven Logic

Kangli Zhao; Anping He; Jun Ma; Lixin Zhang; Lixian Zhu; Qunxi Dong; Fuze Tian; Qingguo Zhou; Qinglin Zhao

doi:10.1109/TCSS.2025.3632912

Hyper-Parallel Superscalar Asynchronous RISC-V Processor Based on Event-Driven Logic

Kangli Zhao
, Anping He
, Jun Ma
, Lixin Zhang
, Lixian Zhu
, Qunxi Dong
, Fuze Tian^*
, Qingguo Zhou^*
, Qinglin Zhao^*

^*此作品的通讯作者

人工智能学院

Lanzhou University
Beijing Institute of Technology

科研成果: 期刊稿件 › 文章 › 同行评审

摘要

Event-driven neuromorphic computing involves sparse and asynchronous signal activity, which leads to irregular computation patterns and fine-grained concurrency. As a result, processing architectures need to support both high parallelism and energy efficiency. Among existing architectural solutions, superscalar designs exhibit significant potential for addressing high parallelism demands. However, conventional superscalar processors, which rely on synchronous circuits, maintain high-frequency clocking at all times, leading to substantial power inefficiency in sparse computation scenarios. To address this issue, we propose an asynchronous superscalar architecture that replaces global clocking with fully local handshake-based control, implemented using a bundled-data asynchronous protocol. The design supports decoding of up to 64 scalar instructions per cycle and implements the RISC-V RV32IMC instruction set. A prototype was fabricated using a 110 nm complementary metal oxide semiconductor (CMOS) process and was evaluated through post-layout simulation. Operating at 1.2 V, the processor delivers a peak INT8 throughput of 669.4 GOPS, with a static power consumption of 421 mW.

源语言	英语
页（从-至）	2450-2460
页数	11
期刊	IEEE Transactions on Computational Social Systems
卷	13
期	2
DOI	https://doi.org/10.1109/TCSS.2025.3632912
出版状态	已出版 - 2026

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title = "Hyper-Parallel Superscalar Asynchronous RISC-V Processor Based on Event-Driven Logic",

abstract = "Event-driven neuromorphic computing involves sparse and asynchronous signal activity, which leads to irregular computation patterns and fine-grained concurrency. As a result, processing architectures need to support both high parallelism and energy efficiency. Among existing architectural solutions, superscalar designs exhibit significant potential for addressing high parallelism demands. However, conventional superscalar processors, which rely on synchronous circuits, maintain high-frequency clocking at all times, leading to substantial power inefficiency in sparse computation scenarios. To address this issue, we propose an asynchronous superscalar architecture that replaces global clocking with fully local handshake-based control, implemented using a bundled-data asynchronous protocol. The design supports decoding of up to 64 scalar instructions per cycle and implements the RISC-V RV32IMC instruction set. A prototype was fabricated using a 110 nm complementary metal oxide semiconductor (CMOS) process and was evaluated through post-layout simulation. Operating at 1.2 V, the processor delivers a peak INT8 throughput of 669.4 GOPS, with a static power consumption of 421 mW.",

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AU - Zhao, Kangli

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AU - Zhu, Lixian

AU - Dong, Qunxi

AU - Tian, Fuze

AU - Zhou, Qingguo

AU - Zhao, Qinglin

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AB - Event-driven neuromorphic computing involves sparse and asynchronous signal activity, which leads to irregular computation patterns and fine-grained concurrency. As a result, processing architectures need to support both high parallelism and energy efficiency. Among existing architectural solutions, superscalar designs exhibit significant potential for addressing high parallelism demands. However, conventional superscalar processors, which rely on synchronous circuits, maintain high-frequency clocking at all times, leading to substantial power inefficiency in sparse computation scenarios. To address this issue, we propose an asynchronous superscalar architecture that replaces global clocking with fully local handshake-based control, implemented using a bundled-data asynchronous protocol. The design supports decoding of up to 64 scalar instructions per cycle and implements the RISC-V RV32IMC instruction set. A prototype was fabricated using a 110 nm complementary metal oxide semiconductor (CMOS) process and was evaluated through post-layout simulation. Operating at 1.2 V, the processor delivers a peak INT8 throughput of 669.4 GOPS, with a static power consumption of 421 mW.

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Hyper-Parallel Superscalar Asynchronous RISC-V Processor Based on Event-Driven Logic

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