A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI

Yiyang Yuan; Zhongyi Sun; Yiming Yang; Xinghua Wang; Xiaoran Li; Cailian Ma; Qirui Chen; Meini Tang; Xi Wei; Hao Wu; Haitao Wang; Qihao Liu; Chengying Chen; Jinshan Yue; Pui In Mak; Feng Zhang

doi:10.1109/JSSC.2026.3668132

A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI

Yiyang Yuan
, Zhongyi Sun
, Yiming Yang
, Xinghua Wang^*
, Xiaoran Li^*
, Cailian Ma
, Qirui Chen
, Meini Tang
, Xi Wei
, Hao Wu
, Haitao Wang
, Qihao Liu
, Chengying Chen
, Jinshan Yue
, Pui In Mak
, Feng Zhang^*

^*Corresponding author for this work

CAS - Institute of Microelectronics
Beijing Institute of Technology
Shandong SinoChip Semiconductors Company Ltd.
Xiamen University of Technology
University of Macau

Research output: Contribution to journal › Article › peer-review

Abstract

With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to enhance the energy efficiency of FP CIM computation. This work employs: 1) a hybrid-domain CIM macro structure that fully utilizes the advantages of digital and analog CIM paradigms; 2) a logarithm bit-width zero-canceling residual analog-digital convertor (ADC) to minimize the ADC overhead and improve throughput; and 3) an outer product-based FP/INT CIM architecture to eliminate the need for a large fan-in multi-level adder tree and reduce the transmission delay. A fabricated 28-nm 192-Kb INT/FP CIM macro achieves maximum peak energy efficiency of 72.12 TFLOPS/W and maximum area efficiency of 2.21 TFLOPS/m². The accuracy loss of running ResNet-18 on the CIFAR-100 dataset with BF16IN-BF16W-BF16OUT is 0.05%.

Original language	English
Journal	IEEE Journal of Solid-State Circuits
DOIs	https://doi.org/10.1109/JSSC.2026.3668132
Publication status	Accepted/In press - 2026
Externally published	Yes

Keywords

Artificial intelligence (AI)
SRAM
computing-in-memory (CIM)
floating-point (FP)
hybrid-domain

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10.1109/JSSC.2026.3668132

Cite this

Yuan, Y., Sun, Z., Yang, Y., Wang, X., Li, X., Ma, C., Chen, Q., Tang, M., Wei, X., Wu, H., Wang, H., Liu, Q., Chen, C., Yue, J., Mak, P. I., & Zhang, F. (Accepted/In press). A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/JSSC.2026.3668132

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title = "A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI",

abstract = "With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to enhance the energy efficiency of FP CIM computation. This work employs: 1) a hybrid-domain CIM macro structure that fully utilizes the advantages of digital and analog CIM paradigms; 2) a logarithm bit-width zero-canceling residual analog-digital convertor (ADC) to minimize the ADC overhead and improve throughput; and 3) an outer product-based FP/INT CIM architecture to eliminate the need for a large fan-in multi-level adder tree and reduce the transmission delay. A fabricated 28-nm 192-Kb INT/FP CIM macro achieves maximum peak energy efficiency of 72.12 TFLOPS/W and maximum area efficiency of 2.21 TFLOPS/m2. The accuracy loss of running ResNet-18 on the CIFAR-100 dataset with BF16IN-BF16W-BF16OUT is 0.05\%.",

keywords = "Artificial intelligence (AI), SRAM, computing-in-memory (CIM), floating-point (FP), hybrid-domain",

author = "Yiyang Yuan and Zhongyi Sun and Yiming Yang and Xinghua Wang and Xiaoran Li and Cailian Ma and Qirui Chen and Meini Tang and Xi Wei and Hao Wu and Haitao Wang and Qihao Liu and Chengying Chen and Jinshan Yue and Mak, \{Pui In\} and Feng Zhang",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2026",

doi = "10.1109/JSSC.2026.3668132",

language = "English",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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AU - Yuan, Yiyang

AU - Sun, Zhongyi

AU - Yang, Yiming

AU - Wang, Xinghua

AU - Li, Xiaoran

AU - Ma, Cailian

AU - Chen, Qirui

AU - Tang, Meini

AU - Wei, Xi

AU - Wu, Hao

AU - Wang, Haitao

AU - Liu, Qihao

AU - Chen, Chengying

AU - Yue, Jinshan

AU - Mak, Pui In

AU - Zhang, Feng

PY - 2026

Y1 - 2026

N2 - With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to enhance the energy efficiency of FP CIM computation. This work employs: 1) a hybrid-domain CIM macro structure that fully utilizes the advantages of digital and analog CIM paradigms; 2) a logarithm bit-width zero-canceling residual analog-digital convertor (ADC) to minimize the ADC overhead and improve throughput; and 3) an outer product-based FP/INT CIM architecture to eliminate the need for a large fan-in multi-level adder tree and reduce the transmission delay. A fabricated 28-nm 192-Kb INT/FP CIM macro achieves maximum peak energy efficiency of 72.12 TFLOPS/W and maximum area efficiency of 2.21 TFLOPS/m2. The accuracy loss of running ResNet-18 on the CIFAR-100 dataset with BF16IN-BF16W-BF16OUT is 0.05%.

AB - With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to enhance the energy efficiency of FP CIM computation. This work employs: 1) a hybrid-domain CIM macro structure that fully utilizes the advantages of digital and analog CIM paradigms; 2) a logarithm bit-width zero-canceling residual analog-digital convertor (ADC) to minimize the ADC overhead and improve throughput; and 3) an outer product-based FP/INT CIM architecture to eliminate the need for a large fan-in multi-level adder tree and reduce the transmission delay. A fabricated 28-nm 192-Kb INT/FP CIM macro achieves maximum peak energy efficiency of 72.12 TFLOPS/W and maximum area efficiency of 2.21 TFLOPS/m2. The accuracy loss of running ResNet-18 on the CIFAR-100 dataset with BF16IN-BF16W-BF16OUT is 0.05%.

KW - Artificial intelligence (AI)

KW - SRAM

KW - computing-in-memory (CIM)

KW - floating-point (FP)

KW - hybrid-domain

UR - https://www.scopus.com/pages/publications/105031967060

U2 - 10.1109/JSSC.2026.3668132

DO - 10.1109/JSSC.2026.3668132

M3 - Article

AN - SCOPUS:105031967060

SN - 0018-9200

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

ER -

A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI

Abstract

Keywords

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