A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI

TY - JOUR

T1 - A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI

AU - Yuan, Yiyang

AU - Sun, Zhongyi

AU - Yang, Yiming

AU - Wang, Xinghua

AU - Li, Xiaoran

AU - Ma, Cailian

AU - Chen, Qirui

AU - Tang, Meini

AU - Wei, Xi

AU - Wu, Hao

AU - Wang, Haitao

AU - Liu, Qihao

AU - Chen, Chengying

AU - Yue, Jinshan

AU - Mak, Pui In

AU - Zhang, Feng

N1 - Publisher Copyright: © 2026 IEEE.

PY - 2026/8/1

Y1 - 2026/8/1

N2 - With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to enhance the energy efficiency of FP CIM computation. This work employs: 1) a hybrid-domain CIM macro structure that fully utilizes the advantages of digital and analog CIM paradigms; 2) a logarithm bit-width zero-canceling residual analog-digital convertor (ADC) to minimize the ADC overhead and improve throughput; and 3) an outer product-based FP/INT CIM architecture to eliminate the need for a large fan-in multi-level adder tree and reduce the transmission delay. A fabricated 28-nm 192-Kb INT/FP CIM macro achieves maximum peak energy efficiency of 72.12 TFLOPS/W and maximum area efficiency of 2.21 TFLOPS/mm2. The accuracy loss of running ResNet-18 on the CIFAR-100 dataset with BF16IN-BF16W-BF16OUT is 0.05%.

AB - With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to enhance the energy efficiency of FP CIM computation. This work employs: 1) a hybrid-domain CIM macro structure that fully utilizes the advantages of digital and analog CIM paradigms; 2) a logarithm bit-width zero-canceling residual analog-digital convertor (ADC) to minimize the ADC overhead and improve throughput; and 3) an outer product-based FP/INT CIM architecture to eliminate the need for a large fan-in multi-level adder tree and reduce the transmission delay. A fabricated 28-nm 192-Kb INT/FP CIM macro achieves maximum peak energy efficiency of 72.12 TFLOPS/W and maximum area efficiency of 2.21 TFLOPS/mm2. The accuracy loss of running ResNet-18 on the CIFAR-100 dataset with BF16IN-BF16W-BF16OUT is 0.05%.

KW - Artificial intelligence (AI)

KW - SRAM

KW - computing-in-memory (CIM)

KW - floating-point (FP)

KW - hybrid-domain

UR - https://www.scopus.com/pages/publications/105031967060

U2 - 10.1109/JSSC.2026.3668132

DO - 10.1109/JSSC.2026.3668132

M3 - Article

AN - SCOPUS:105031967060

SN - 0018-9200

VL - 61

SP - 4450

EP - 4462

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 8

ER -